As a result of the continuous developments in integrated circuits (ICs), the full adders contribute to a substantial portion of any circuit design's area and power. The various units of an IC that consume power are logic implementation, full adders, flip flops, RAM, clock tree and integrated clock gating (ICG) cells. The full adders consume 30-40% of the total area and 30-40% of the total power in a typical digital design.
The power consumed by a full adder is directly proportional to a number of transistors used for implementing the full adder. Thus, it is apparent that with reduced transistor count, the power consumed by the full adder can also be reduced. Also, a reduction in area of the full adder will directly translate to reduction in chip area and saving of costs. Also, since the full adders are most critical in the data path, improving the area and power consumed by the full adder improves the performance of the digital designs using the full adder.